Octane2 setup and running IRIX
Octane2 setup and running IRIX

The Octane and its later version, the **Octane 2**, code named Speed Racer, is a high end workstation marketed by Silicon Graphics between 1996 and 2004. It is an SMP-capable (dual CPU) machine running the MIPS R10000 to R14000 series of processors. The main differences between the Octane2 and the Octane are configuration-related. The Octane 2 has upgraded motherboard, power supply, front plane and graphics options, but it's entirely possible to retrofit these upgrades to a regular Octane, creating the "Octane 1.5" as many have popularly dubbed it.

A late-model Octane2 with the 'sgi' logo
A late-model Octane2 with the 'sgi' logo


The Octane's system-board is designated as IP30. The system is based on SGI's Xtalk (Pronounced Cross-talk) architecture. This means it does not use a system bus; instead it has a router XBOW (Pronounced cross-bow) that connects any two of its ports. One of the ports is used for the processor and memory subsystem, one is available for PCI (actually PCI-64) expansion and four are XIO slots (packet-based high-bandwidth bus, somewhat similar to HyperTransport). This makes it very similar to a single node of the SGI Origin 200 system.

The XIO is here and there bridged to PCI-64, using a chip named BRIDGE. The places where it happens include the system board (for the IOC3 multi-I/O chip, two ISP1040B SCSI controllers and RAD1 audio), MENET cards (four IOC3s) and the PCI cage (used for PCI cards in Octane). ARCS is provided as the boot firmware, similar to all contemporary SGI computer systems.


The Octane series has single and dual CPU modules. A second CPU cannot be added to a single CPU module, therefore upgrading to two requires replacing the entire CPU module.

What follows is a table of all known models:

Processor Cache Single (Mhz) Dual (Mhz)
R10000SC 1MB 175, 195, 225, 250 175, 195, 225, 250
R12000SC 2MB 270, 300, 400 270, 300, 400
R12000SCA 2MB 360, 400 360, 400
R14000SCA 2MB 550, 600 550, 600


The Octane allows 256 MB to 8 GB of system memory, using proprietary 200-pin DIMMs. There are two system board revisions. The first revision (part number 030-0887-00x, usually distinguished by a black handle) only supports 2GB of RAM while the later one (part number 030-1467-001, with a silver handle) supports up to 8GB. The -0887 revision of the mainboard will work with all 32-128 MB DIMMS and the stacked variant of 256MB DIMMS, but not the later single-board version (SGI P/N 9010036). The memory subsystem has vast reserves of bandwidth that can be directly served by the Xbow router to any XIO card.

The Octane's memory controller is aptly named HEART. It acts as a controller between the processor, the memory (SDRAM) and the XIO bus.


Graphics on the Octane are provided by a series of cards: SI, SI+T, SSI, MXI. These are updated XIO versions of Solid Impact (SI), High Impact (SI+T) and Maximum Impact (MXI) from the SGI Indigo2 that were internally designated by SGI as 'MARDIGRAS'. The boards were accelerated and reengineered with faster geometry engine and texture modules to create their new versions: SE, SE+T, SSE, MXE. The SI/SE provides 13.5MB of framebuffer memory while the SSE and MXE have a 27MB framebuffer. The '+T' indicates an additional high speed RDRAM texture board which gives 4MB of texture memory, which is practically indispensable, though quite expensive and fragile. The SI/SE+T has one texture board while the MXI/MXE has 2 texture boards, however, the 2 boards in the MXI/MXE do not double the available texture memory to the system. It just doubles the texture performance.

Later Octanes and Octane 2s support the SGI VPro graphics board series, designated 'ODYSSEY'. The first VPro series cards were the V6 and V8. The main differentiator being that the V6 has 32MB of RAM (unlike the MARDI GRAS option, framebuffer memory and texture memory come from the same pool) and V8 having 128MB. Later, the V10 (32MB) and V12 (128MB) were introduced. The main difference with the new VPro V10/V12 series is that they had double the geometry performance of the older V6/V8. V6 and V10 can have up to 8MB RAM allocated to textures (2X more than the textured-enabled MARDIGRAS options), while V8 and V12 can have up to 108MB RAM used for textures.

The VPro graphics subsystem consists of an SGI proprietary chip set and associated software. The chip set consists of the buzz ASIC, pixel blaster and jammer (PB&J) ASIC, and associated SDRAM.

The buzz ASIC is a single-chip graphics pipeline. It operates at 251 MHz and contains on-chip SRAM. The buzz ASIC has three interfaces:

  • Host (16-bit, 400-MHz peer-to-peer XIO link)
  • SDRAM (The SDRAM is 32 MB (V6 or V10) or 128 MB (V8 or V12); the memory bus operates at half the speed of the buzz ASIC.)


As with the MARDIGRAS boards, all VPro boards support OpenGL in hardware (MARDIGRAS is OpenGL 1.1 + SGI Extensions, while VPro upgraded support to OpenGL 1.2) and OpenGL ARB imaging extensions, allowing for hardware acceleration of numerous imaging operations at real-time rates.

Compatibility: The V6/V8 boards require an XBOW 1.3 board, but the V10/V12 boards do appear to require an XBow 1.4 frontplane.


The Octane supports Ultra Wide SCSI devices and has two SCSI controllers. System can have up to three internal 3.5" SCSI SCA devices. Octanes use special mounting sleds for the hard drives which are compatible with Origin 2000, Origin 200 and Onyx2. The system also has external Ultra Wide SCSI bus.

The aptly named HEART is the core of the Octane. It integrates a SDRAM memory controller, a XIO device, an interrupt controller and a processor bus interface for up to four R10000-class processors.

The HEART can be accessed in two ways from the processor. The first one is through the PIU (Programmed I/O Unit) at 0xFF0000 in processor physical address space. The other one is at widget 8 in XIO address space. The only one way available to other XIO devices is through the widget interface, so the Interrupt Status Set register is mapped there at address 0x80.

The HEART contains a SDRAM memory controller with ECC. ECC errors are signaled to the CPUs by interrupts.

The XIO bridge is one of the main functions of the HEART. There are three access windows defined for each XIO widget number. There is a window at 0x10000000+ W*0x1000000 for widget number W, a window at 0x800000000+W*0x80000000 and a window at 0x1000000000+W*0x1000000000.

Note that XIO accesses are deeply pipelined by default. Due to that fact, writing to any XIO widget may not have any effect for several hundred cycles. To guarantee finalization of all posted writes it is required to read the widget flush register.

The XIO bridge in HEART provides also some Flow Control features for two channels. They allow to schedule a hiwater IRQ for any given XIO register address. If the register is an input to a FIFO, as is the case with the IMPACT graphics board, exceeding a prescribed number of writes to this register would cause a FIFO hiwater condition. As you already know, the XIO writes are posted and not immediately executed. Catching the hiwater condition in the HEART and not in the card allows to trap it in a more reliable way.

The HEART interrupt controller is visible from the PIU as a set of registers: interrupt mask registers for all processors (IMR0:3), an interrupt status register (ISR) and ISR clear and set registers that allow atomic manipulation of the ISR.

The XIO side consists of a single register 0x80 that can accept either an atomic ISR bit set command or an atomic ISR bit clear command. These commands cause asserting and deasserting IP7:2 bits in the CPUs whose IMRs contain the bit in question.

A small part of the HEART is a programmable interval timer, consisting of 24-bit COUNT and COMPARE registers. The IRQ can be delivered only to the IP6 bit, which is the highest-priority CPU interrupt except internal CPU timer and HEART error IRQs. The timer counts at 12.5 MHz, every 8th internal HEART cycle (1/4th of the XIO frequency).

The HEART controls also the Number In a Can associated with processor modules. It features a standard SGI issue MicroLAN controller.

A typical Octane2
A typical Octane2

Octane 2 Upgrades

Octane 2 has a revised power supply, system-board and XBOW. Octane 2 also shipped with VPro graphics and supports all available VPro cards (V6, V8, V10 and V12). Later revision Octanes also included some of the improvements mentioned.

The case is blue instead of the green used by the original, the plastics are compatible between the two and the chassis is identical.

Operating System Support

The Octane was first supported by IRIX version 6.4 with IMPACT or "Mardi Gras" graphics (SI/SSI/MXI and later Enhanced versions). Support for VPro or "Odyssey" graphics in Octanes was introduced with IRIX 6.5.10 for V6/V8, and in IRIX 6.5.11 for V10/V12. (Drivers were released to support V10/V12 under 6.5.10.) All versions of IRIX through 6.5.30 include support for the Octane family machines.